1. Field of the Invention
The present invention generally relates to a frequency dividing circuit, and more particularly to a glitch-free frequency dividing circuit capable of preventing the generation of glitches when the divisor is switched.
2. Description of the Prior Art
A frequency dividing circuit is used to divide a high frequency pulse by an integer divisor and to output a required low frequency pulse to feed other circuits. However, a general frequency dividing circuit with divisor switching function does not provide a detection circuit to monitor and control the timing of switching the divisor, therefore, a glitch may occur in the output signal when the divisor is switched. The glitch may cause malfunction during the sequential operation of the circuit. Moreover, not all frequency dividing circuits provide an output signal with a duty cycle of 50% that limits the application of the frequency dividing circuit.
Accordingly, the primary object of the present invention is to provide a glitch-free frequency dividing circuit which is capable of preventing the generation of glitches while switching the divisor.
It is another object of the present invention is to provide a glitch-free frequency dividing circuit which has a detection circuit to monitor and control the timing to switch the divisor so as to prevent the glitch generation.
It is still another object of the present invention to provide a glitch-free frequency dividing circuit that operates when the divisor is either even or odd number that will not generate glitches.
It is still another object of the present invention to provide a glitch-free frequency dividing circuit capable of providing an output signal with a duty cycle of 50%.
In order to achieve the foregoing objects, the present invention provides a glitch-free frequency dividing circuit comprising a frequency dividing module and a latch module. When the latch module receives a signal for switching the divisor, the state of the output pulse from the frequency dividing module is detected and the control signal is enabled at a proper time (when the output pulse is at the state of xe2x80x9c0xe2x80x9d, for example) such that the output pulse is maintained at the same state. In addition, when the control signal is enabled, a new divisor is latched in a latch register and the frequency dividing module is provided with the latched divisor. The control signal is then disabled. The frequency dividing module counts the reference pulse and then output the pulse divided by the divisor according to the divisor from the latch module.
Other and further features, advantages and benefits of the invention will become apparent in the following description taken in conjunction with the following drawings. It is to be understood that the foregoing general description and following detailed description are exemplary and explanatory but are not to be restrictive of the invention. The accompanying drawings are incorporated in and constitute a part of this application and, together with the description, serve to explain the principles of the invention in general terms.